The invention pertains to semiconductor constructions and methods of forming semiconductor constructions. In particular aspects, the invention pertains to isolation region constructions which can be utilized for, for example, electrically isolating transistor constructions from one another.
Electrical isolation is commonly utilized in semiconductor constructions to alleviate, or prevent, leakage between electrical devices. For instance, it is frequently desired in dynamic random access memory (DRAM) fabrication to avoid sub-threshold leakage between access devices (such as, for example, access transistor constructions). There can be several facets which influence leakage currents between field effect transistor devices, including, for example, junction leakage in source/drain regions; drain-induced barrier lowering (DIBL) due to short gate lengths; gate-induced drain leakage (GIDL) due to high electric fields in a gate overlap region; narrow-width effects; and stress-induced leakage current (SILC) due to a proximity of an isolation region to a device.
A ratio of Ion (drive current) to Ioff (sub-threshold leakage) can be utilized as a figure of merit for determining if access devices are performing adequately. It is found that reducing gate oxide thickness of access devices can improve a sub-threshold behavior of the devices while simultaneously increasing a drive current. However, a threshold voltage of a device reduces with the decrease in gate oxide thickness. Increasing dopant levels in channels of the devices can increase the threshold voltage to an acceptable level and compensate for the reduction in gate oxide thickness, but can increase junction leakage in source/drain regions. Additionally, the increased dopant level in a channel of a device can adversely cause junction capacitance to increase, and reduce the current drive of the device.
It would be desirable to develop new methods for reducing sub-threshold leakage of devices. It would be further desirable if such new methods avoided increasing dopant concentration in channel regions of access devices. Additionally, it would be desirable if such new methods could be utilized for forming structures suitable for electrical isolation in an integrated circuit construction.
In one aspect, the invention encompasses a semiconductor construction which includes a gate layer over a segment of a substrate. The segment can be considered a channel region. The gate layer has a first type majority dopant therein. A pair of conductively-doped diffusion regions are within the substrate adjacent the channel region, and spaced from one another by the channel region. The conductively-doped diffusion regions have a second type majority dopant therein. The majority dopant of the conductively-doped diffusion regions is opposite to the majority dopant of the gate layer. In other words, one of the first and second type dopants is n-type, and the other is p-type. The gate layer can, in particular applications, be electrically connected to a ground associated with the substrate.
In one aspect, the invention encompasses a DRAM array having one or more structures therein which include a gate layer separated from a silicon-containing substrate by an intervening insulative material. The gate layer is doped to at least 1xc3x971017 atoms/cm3 with n-type dopant and is also doped to at least 1xc3x971017 atoms/cm3 with p-type dopant.
The invention also encompasses methods of forming semiconductor constructions.